Method for increasing rate at which a comparator in a metastable condition transitions to a steady state

ABSTRACT

A method for reducing bit errors in an analog to digital converter having an array of comparators. The outputs of first and second comparators are received as in inputs to an Exclusive OR gate. The first and second comparators are separated in the array by a third comparator. The output of the Exclusive OR gate is used to determine if the third comparator is in a metastable condition. If the third comparator is in a metastable condition, the bias current of the latch circuit of the third comparator is increased to increase the rate at which the third comparator transitions to a steady state.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a division of U.S. application Ser. No. 10/226,165filed Aug. 23, 2002, now U.S. Pat. No. 6,727,839, which is incorporatedherein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to high speed, low power comparators.

2. Background Art

Commercialization of the Internet has proven to be a mainspring forincentives to improve network technologies. Development programs havepursued various approaches including strategies to leverage use of theexisting Public Switched Telephone Network and plans to expand use ofwireless technologies for networking applications. Both of theseapproaches (and others) entail the conversion of data between analog anddigital formats. Therefore, it is expected that analog-to-digitalconverters (ADCs) and digital-to-analog converters (DACs) will continueto perform critical functions in many network applications.

Because ADCs find uses in a wide variety of applications, design ofthese circuits has evolved along many paths to yield several distinctarchitectures, including “delta sigma,” “successive approximation,”“pipelined,” “subranging,” “folding,” and “flash.” Comparators are thebasic building block in each of these designs, and somearchitectures—such as pipelined, subranging, folding, and flash—use anarray of comparators.

For example, FIG. 1 is a block diagram of an exemplary conventionaltwo-bit flash ADC 100. ADC 100 comprises a first comparator “A” 102, asecond comparator “B” 104, a third comparator “C” 106, a priorityencoder 108, a first resistor “R₁” 110, a second resistor “R₂” 112, athird resistor “R₃” 114, and a fourth resistor “R₄” 116. Each of R₁ 110,R₂ 112, R₃ 114, and R₄ 116 has the same measure of resistance. R₁ 110,R₂ 112, R₃ 114, and R₄ 116 are connected in series between an analogground “V_(AG)” 118 and a first supply voltage “V_(DD)” 120.(Alternatively, analog ground V_(AG) 118 can be replaced by a secondsupply voltage “V_(SS)”.) R₁ 110 is connected between V_(AG) 118 and afirst node “N₁” 122. R₂ 112 is connected between N₁ 122 and a secondnode “N₂” 124. R₃ 114 is connected between N₂ 124 and a third node “N₃”126. R₄ 116 is connected between N₃ 126 and V_(DD) 120. In thisconfiguration, the voltage at N₁ 122 (the reference voltage ofcomparator A 102) is equal to V_(DD)/4, the voltage at N₂ 124 (thereference voltage of comparator B 104) is equal to V_(DD)/2, and thevoltage at N₃ 126 (the reference voltage of comparator C 106) is equalto 3V_(DD)/4.

The inverting terminals of comparators A 102, B 104, and C 106 areconnected to, respectively, N₁ 122, N₂ 124, and N₃ 126. An analog signal“x” 128 is received at an input 130, which is connected to thenoninverting terminals of comparators A 102, B 104, and C 106. Aquantized signal is produced at the output terminal of each comparator.Quantized signals “w₁” 132, “w₂” 134, and “w₃” 136 are produced at theoutput terminals of, respectively, comparators A 102, B 104, and C 106.Each quantized signal has a voltage with a value “LOW” or a value “HIGH”depending upon whether a corresponding value of the voltage of analogsignal x 128 is less than (or equal to) or greater than the voltage atthe inverting terminal of the corresponding comparator (i.e., thereference voltage of the comparator). For example, when the value of thevoltage of analog signal x 128 is less than or equal to V_(DD)/4, thevalues of the voltages of w₃ 136, w₂ 134, and w₁ 132 are equal to,respectively, LOW, LOW, and LOW. When the value of the voltage of analogsignal x 128 is less than or equal to V_(DD)/2, but greater thanV_(DD)/4, the values of the voltages of w₃ 136, w₂ 134, and w₁ 132 areequal to, respectively, LOW, LOW, and HIGH. When the value of thevoltage of analog signal x 128 is less than or equal to 3V_(DD)/4, butgreater than V_(DD)/2, the values of the voltages of w₃ 136, w₂ 134, andw₁ 132 are equal to, respectively, LOW, HIGH, and HIGH. When the valueof the voltage of analog signal x 128 is less than or equal to V_(DD),but greater than 3V_(DD)/4, the values of the voltages of w₃ 136, w₂134, and w₁ 132 are equal to, respectively, HIGH, HIGH, and HIGH.

The output terminals of comparators A 102, B 104, and C 106 areconnected to priority encoder 108. Quantized signals w₁ 132, w₂ 134, andw₃ 136 are received by priority encoder 108, which processes them toproduce, at an output 138, a two-bit digital signal “y” comprising aleast significant bit (LSB) signal “y₁” 140 and a most significant bit(MSB) signal “y₂” 142.

The skilled artisan will appreciate that, with additional comparatorsand resistors and by using a priority encoder capable of processingadditional quantized signals, flash ADC 100 can be modified so thatdigital signal y comprises more than two bit signals. Alternatively,flash ADC 100 can be modified so that digital signal y comprises one bitsignal.

Implementations of comparators A 102, B 104, and C 106 often usecurrent-mode latch circuits. FIG. 2 is a schematic diagram of anexemplary conventional current-mode latch circuit 200 that can be usedin an implementation of any of comparators A 102, B 104, or C 106. Latchcircuit 200 comprises a cross-connected pair of transistors 202connected between a reset switch 204 and first supply voltage V_(SS)118. Preferably, cross-connected pair 202 comprises a first NMOSFET(n-channel Metal Oxide Semiconductor Field Effect Transistor) “M₁” 206and a second NMOSFET “M₂” 208. Ideally, M₁ 206 and M₂ 208 are matchedtransistors. Preferably, each of M₁ 206 and M₂ 208 has a gain greaterthan one. However, cross-connected pair 202 can function if the productof the individual gains of M₁ 206 and M₂ 208 (i.e., the loop gain) isgreater than one. The gate terminal of M₂ 208 is connected to the drainterminal of M₁ 206 at a first port “N₄” 210. The gate terminal of M₁ 206is connected to the drain terminal of M₂ 208 at a second port “N₅” 212.The source terminals of M₁ 206 and M₂ 208 are together connected toanalog ground V_(AG) 118. Preferably, reset switch 204 comprises a thirdNMOSFET “M₃” 214. The source terminal of M₃ 214 is connected to thedrain terminal of one of M₁ 206 or M₂ 208; the drain terminal of M₃ 214is connected the drain terminal of the other of M₁ 206 or M₂ 208. Aclock waveform “Ck” 216 is applied to the gate terminal of M₃ 214. Ck216 cycles between an “UP” voltage and an “DOWN” voltage at a samplingfrequency.

The skilled artisan will appreciate that M₁ 206, M₂ 208, and M₃ 214 canalso be realized in other field effect, junction, or combinationtransistor technologies. In general, reset switch 204 can be realized ina variety of switch technologies, including microelectromechanicalembodiments. Latch circuit 200 can also be used for other applications.

For each latch circuit 200 in ADC 100, quantized signal “w” (e.g., w₁132, w₂ 134, or w₃ 136) is produced as an output voltage at N₄ 210 or N₅212. Latch circuit 200 is often preceded by an input stage (not shown)that includes a differential amplifier so that the voltage of analogsignal x 128, applied at the noninverting terminal of the comparator,can be compared with the voltage at the inverting terminal of thecomparator. For example, the voltage of analog signal x 128 is comparedwith V_(DD)/4, for comparator A 102; V_(DD)/2, for comparator B 104; and3V_(DD)/4, for comparator C 106.

For each latch circuit 200 in ADC 100, the input stage produces adifferential current signal comprising a first current signal “i₁” 218and a second current signal “i₂” 220. First and second current signalsi₁ 218 and i₂ 220 each comprise a bias current “i_(b)” and a signalcurrent “i_(s)”. The relationship between bias current i_(b) and signalcurrent i_(s) in first current signal i₁ 218 can be expressed as shownin Eq. (1):i ₁ =i _(b)+(1/2)(i _(s)),  Eq. (1)while the relationship between bias current i_(b) and signal currenti_(s) in second current signal i₂ 220 can be expressed as shown in Eq.(2):i ₂ =i _(b)−(1/2)(i _(s)).  Eq. (2)The differential amplifier is configured so that first current signal i₁218 increases and decreases in response to, respectively, the rise anddrop of the voltage of analog signal x 128, while second current signali₂ 220 increases and decreases in response to, respectively, the dropand rise of the voltage of analog signal x 128. Thus, first and secondcurrent signals i₁ 218 and i₂ 220 always change currents in oppositedirections, but the sum of first and second current signals i₁ 218 andi₂ 220 remains equal to twice the bias current i_(b).

For each latch circuit 200 in ADC 100, the differential amplifier isconfigured so that no signal current i_(s) is produced when the voltageof analog signal x 128, applied at the noninverting terminal of thecomparator, equals the voltage at the inverting terminal of thecomparator. For example, for comparator A 102, no signal current i_(s)is produced when the voltage of analog signal x 128 equals V_(DD)/4; forcomparator B 104, no signal current i_(s) is produced when the voltageof analog signal x 128 equals V_(DD)/2; and for comparator C 106, nosignal current i_(s) is produced when the voltage of analog signal x 128equals 3V_(DD)/4.

In latch circuit 200, first current signal i₁ 218 and second currentsignal i₂ 220 are received as input current signals at, respectively, N₄210 and N₅ 212. When the voltage of Ck 216 is UP (i.e, the reset phase),M₃ 214 connects N₄ 210 with N₅ 212, so that the steady state voltages atboth nodes are equal, and bias current i_(b) flows through each of M₁206 and M₂ 208. Parasitic capacitances at each of nodes N₄ 210 and N₅212 are charged by bias current i_(b) that flows through each of M₁ 206and M₂ 208. The skilled artisan will appreciate that the parasiticcapacitance at, for example, N₄ 210, includes the gate-to-sourcecapacitance of M₂ 208, the drain-to-substrate capacitance of M₁ 206, thedrain-to-substrate capacitance of M₃ 214, and the capacitance of thewiring connecting circuit devices. Bias current i_(b) charges theparasitic capacitances at each of nodes N₄ 210 and N₅ 212 so that thevoltages at N₄ 210 and N₅ 212 are at a metastable “MID” value that isbetween LOW and HIGH. The gate and drain terminals of M₁ 206 and M₂ 208are connected together. M₁ 206 and M₂ 208 are sized so that, under theseconditions, they operate in “ON” states.

When the voltage of Ck 216 is DOWN (i.e., the sampling phase), thestates of M₁ 206 and M₂ 208 are controlled by first and second currentsignals i₁ 218 and i₂ 220. For example, when first current signal i₁ 218is greater than bias current i_(b) and second current signal i₂ 220 isless than bias current i_(b), a transient is initiated to force M₁ 206to operate in an “OFF” state, while M₂ 208 remains operating in an ONstate. The course of this transient depends on how first and secondcurrent signals i₁ 218 and i₂ 220 change during the sampling phase. IfM₁ 206 is turned OFF and the parasitic capacitances at N₄ 210 are fullycharged by first current signal i₁ 218 (i.e., at a new steady state),the voltage at N₄ 210 is HIGH and the voltage at N₅ 212 is LOW.

It is a characteristic of latch circuit 200 that the port (i.e., N₄ 210or N₅ 212) receiving the current signal (i.e., i₁ 218 or i₂ 220) that isgreater than bias current i_(b) requires more time to reach its newsteady state voltage than the port receiving the current signal that isless than bias current i_(b). However, if first and second currentsignals i₁ 218 and i₂ 220 both have values near to that of bias currenti_(b) (i.e., small signal current is), it is possible that the outputvoltage (at N₄ 210 or N₅ 212) may not reach LOW or HIGH before the endof the sampling phase, but remain in a metastable condition. Such asituation is more likely to occur if Ck 216 cycles at a high samplingfrequency. In this situation, the quantized signal (i.e., w₁ 132, w₂134, or w₃ 136) produced by the comparator associated with latch circuit200 (i.e., comparator A 102, B 104, or C 106) does not registered as adigital input to priority encoder 108. Consequently, ADC 100 does notproduce a digital signal y. Such a “non-decision” is referred to as a“bit error”. Bit errors can adversely effect the performance of a systemthat uses the digital output of ADC 100.

Bit errors can be reduced by increasing bias current i_(b) so that onlya small signal current i_(s) is needed to force the port (i.e., N₄ 210or N₅ 212) receiving the current signal (i.e., i₁ 218 or i₂ 220) that isgreater than bias current i_(b) to reach its new steady state voltage.This increases the overall speed of latch circuit 200. However,increasing bias current i_(b) can decrease the signal-to-noise ratio ofADC 100. Moreover, increasing bias current i_(b) in all of thecomparators of ADC 100 causes ADC 100 to dissipate more power,particularly because each comparator draws twice the bias current i_(b)during both the sampling and the reset phases. Such a situation isundesirable where ADC 100 is employed in a system that demands low powerconsumption, such as a portable wireless application. What is needed isa technique to identify which comparator, in the array of comparators,is in a metastable condition, and to increase the rate at which theidentified comparator transitions to a steady state.

BRIEF SUMMARY OF THE INVENTION

The present invention relates to high speed, low power comparators. Inan array of comparators, the present invention provides a technique toidentify which comparator is in a metastable condition, and to increasethe rate at which the identified comparator transitions to a steadystate. A bias current is provided to the identified comparator in themetastable condition, such that the rate at which the comparator in themetastable condition transitions to the steady state is increased.

In an embodiment, the bias current is provided by controlling a currentoutput from a variable current source that provides the bias current fora latch circuit of the identified comparator in the metastablecondition.

In another embodiment, the comparator in the metastable condition isidentified by comparing a characteristic of a first comparator of thearray of comparators with a characteristic of a second comparator of thearray of comparators. The first comparator and the second comparator areseparated in the array of comparators by a third comparator in the arrayof comparators. It is determined if the third comparator is thecomparator in the metastable condition based on the comparedcharacteristics. Preferably, the characteristics are compared byreceiving the first and second characteristics as inputs to an ExclusiveOR gate.

In yet another embodiment, the bias current is provided by controlling acurrent output from a variable current source that provides the biascurrent for a latch circuit of the identified comparator in themetastable condition with an output of an Exclusive OR gate.

In still another embodiment, the bias current is provided by connectinga first current source in parallel with a second current source toincrease the bias current for a latch circuit of the identifiedcomparator in the metastable condition. Preferably, a switch thatconnects the first current source in parallel with the second currentsource is controlled by an output of an Exclusive OR gate.

The present invention also provides a method to increase, in an array ofcomparators that includes a first, a second, and a third comparator, arate at which the third comparator transitions to a steady state. Anoutput of the first comparator is compared with an output of the secondcomparator, and a bias current is provided to the third comparator basedon the compared first and second outputs.

In an embodiment, the outputs are compared by receiving the first andsecond outputs as inputs to an Exclusive OR gate. Preferably, a variablecurrent source that provides the bias current for a latch circuit of thethird comparator is controlled based on an output of an Exclusive ORgate.

In another embodiment, the bias current is provided to the thirdcomparator by connecting a first current source in parallel with asecond current source to increase the bias current for a latch circuitof the third comparator. Preferably, a switch that connects the firstcurrent source in parallel with the second current source is controlledbased on an output of an Exclusive OR gate.

The present invention also comprises an array of comparators comprisinga first, a second, and a third comparator, an Exclusive OR gate having afirst input connected to an output of the first comparator and a secondinput connected to an output of the second comparator, and a variablecurrent source connected to an output of the Exclusive OR gate. Thevariable current source supplies a bias current to the third comparator.Preferably, the output of the Exclusive OR gate produces a signal thatcontrols the variable current source. Preferably, the third comparatoris arranged in the array of comparators between the first comparator andthe second comparator.

In an embodiment, the third compararator comprises a latch circuitconfigured to receive the bias current. Preferably, the latch circuitcomprises a cross connected pair of transistors connected between areset switch and a supply voltage. The latch circuit has a first portcapable of receiving a first current signal and producing a first outputvoltage, and a second port capable of receiving a second current signaland producing a second output voltage. In an embodiment, the crossconnected pair of transistors comprises a first MOSFET and a secondMOSFET configured so that the gate terminal of the first MOSFET isconnected to the drain terminal of the second MOSFET, the gate terminalof the second MOSFET is connected to the drain terminal of said theMOSFET, and the source terminals of the first and the second MOSFETs areconnected to the supply voltage. Preferably, the reset switch comprisesa MOSFET connected between the first port and the second port.

In another embodiment, the array of comparators further comprises asecond Exclusive OR gate having an input connected to an output of thethird comparator, and a second variable current source connected to anoutput of the second Exclusive OR gate. The second variable currentsource supplies a second bias current to the second comparator.

The present invention also comprises an analog to digital converter. Theanalog to digital comparator comprises an array of comparators, apriority encoder, an array of Exclusive OR gates, and an array ofvariable current sources. The array of comparators has respective inputsconfigured to receive an analog signal, and respective outputsconfigured to produce quantized signals responsive to the analog signal.The priority encoder is connected to the array of comparators, and isconfigured to produce a digital signal at an output responsive to thequantized signals. Each Exclusive OR gate of the array of Exclusive ORgates is configured to receive two of the quantized signals. Eachvariable current source of the array of variable current sources isconfigured to provide a bias current to a corresponding comparator ofthe array of comparators, and is controlled by an output of acorresponding Exclusive OR gate of the array of Exclusive OR gates.

In an embodiment, each Exclusive OR gate of the array of Exclusive ORgates produces a logic signal that controls a corresponding variablecurrent source of the array of variable current sources. Preferably,each comparator of the array of comparators includes a latch circuitconfigured to receive a corresponding bias current. In anotherembodiment, the corresponding bias current is capable of being increasedby a corresponding variable current source of the array of variablecurrent sources.

Further embodiments, features, and advantages of the present invention,as well as the structure and operation of the various embodiments of thepresent invention, are described in detail below with reference to theaccompanying figures.

BRIEF DESCRIPTION OF THE FIGURES

The accompanying drawings, which are incorporated herein and form partof the specification, illustrate the present invention and, togetherwith the description, further serve to explain the principles of theinvention and to enable a person skilled in the pertinent art to makeand use the invention.

FIG. 1 is a block diagram of an exemplary conventional two-bit flash ADC100.

FIG. 2 is a schematic diagram of an exemplary conventional current-modelatch circuit 200 that can be used in an implementation of any ofcomparators A 102, B 104, or C 106.

FIG. 3 is a block diagram of an array 300 of current-mode comparatorsconfigured in the manner of an embodiment of the present invention.

FIG. 4A is a schematic diagram of an input stage 400 that can be usedwith latch circuit 200 in an implementation of any of comparators A 102,B 104, or C 106.

FIG. 4B is a schematic diagram of an input stage 450 that can be usedwith latch circuit 200 in an implementation of any of comparators A 102,B 104, or C 106.

FIG. 5 is a block diagram of a portion of an array 500 of current-modecomparators configured in the manner of another embodiment of thepresent invention.

FIG. 6 is a block diagram of a portion of an array 600 of current-modecomparators configured in the manner of yet another embodiment of thepresent invention.

FIG. 7 is a schematic diagram of another current-mode latch circuit 700that can be used in a realization of a comparator of the presentinvention.

FIG. 8 shows a flow chart of a method 800 for increasing, in an array ofcomparators, a rate at which a comparator in a metastable conditiontransitions to a steady state.

FIG. 9 shows a flow chart of a preferred method to identify thecomparator in the metastable condition.

FIG. 10 shows a flow chart of a method 1000 for increasing, in an arrayof comparators that includes a first, a second, and a third comparator,a rate at which the third comparator transitions to a steady state.

The preferred embodiments of the invention are described with referenceto the figures where like reference numbers indicate identical orfunctionally similar elements. Also in the figures, the left-most digitof each reference number identifies the figure in which the referencenumber is first used.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to high speed, low power comparators.Where a functional component of a system—such as, but not limited to, apipelined, subranging, folding, or flash ADC—uses an array ofcomparators, the present invention provides a technique to identifywhich comparator is in a metastable condition, and to increase the rateat which the identified comparator transitions to a steady state.

FIG. 3 is a block diagram of an array 300 of current-mode comparatorsconfigured in the manner of an embodiment of the present invention.Array 300 comprises comparator A 102, comparator B 104, comparator C106, an Exclusive OR gate “XOR” 302, and a variable current source“I_(v)” 304. Quantized signals w₁ 132 and w₃ 136 are received as inputsto XOR 302. XOR 302 produces a logic signal “s” 306 that controlsvariable current source I_(v) 304. Variable current source I_(v) 304augments bias current i_(b) for the latch circuit associated with secondcomparator B 104 in response to the value of logic signal s 306.

The skilled artisan will appreciate that logic signal s 306 equals oneonly if quantized signals w₁ 132 and w₃ 136 have different values. Ifquantized signals w₁ 132 and w₃ 136 have the same values, then logicsignal s 306 equals zero. For example, when the values of the voltagesof w₁ 132 and w₃ 136 are equal to, respectively, LOW and LOW, then logicsignal s 306 is zero. When the values of the voltages of w₁ 132 and w₃136 are equal to, respectively, LOW and HIGH, then logic signal s 306 isone. When the values of the voltages of w₁ 132 and w₃ 136 are equal to,respectively, HIGH and LOW, then logic signal s 306 is one. When thevalues of the voltages of w₁ 132 and w₃ 136 are equal to, respectively,HIGH and HIGH, then logic signal s 306 is zero. The skilled artisan willalso appreciate that such a comparison of quantized signals w₁ 132 andw₃ 136 can be realized by applying them to other types of logic gatesthat are configured in a manner to produce the same result as XOR 302.

The present invention is based on the likelihood that, for example,comparator B 104 will be in a metastable condition when comparator A 102produces quantized signal w₁ 132 with value HIGH and comparator C 106produces quantized signal w₃ 136 with value LOW. In this situation,logic signal s 306 is one and, in response, variable current sourceI_(v) 304 augments bias current i_(b) for the latch circuit associatedwith comparator B 104. Increasing bias current i_(b) increases bothfirst and second current signals i₁ 218 and i₂ 220 and decreases thetime needed for the port (i.e., N₄ 210 or N₅ 212) receiving the currentsignal (i.e., i₁ 218 or i₂ 220) that is greater than bias current i_(b)to reach its new steady state voltage. This decreases the probabilitythat comparator B 104 will remain in a metastable condition and thusreduces the bit error rate (BER).

For example, in ADC 100, if analog signal x 128 is nearly equal toV_(DD)/2, then a small signal current i_(s) is produced for comparator B104, a large positive signal current i_(s) is produced for comparator A102, and a large negative signal current i_(s) is produced forcomparator C 106. In this situation, comparator A 102 quickly producesquantized signal w₁ 132 with value HIGH, and comparator C 106 quicklyproduces quantized signal w₃ 136 with value LOW, but comparator B 104may be slow to produce a digital value for quantized signal w₂ 134before the end of the sampling phase. Increasing bias current i_(b) tothe latch circuit associated with comparator B 104 increases its overallspeed, decreases the likelihood that it will remain in a metastablestate, and reduces the BER.

FIG. 4A is a schematic diagram of an input stage 400 that can be usedwith latch circuit 200 in an implementation of any of comparators A 102,B 104, or C 106. Input stage 400 receives analog signal x 128 andproduces first and second current signals i₁ 218 and i₂ 220, which arereceived by latch circuit 200. Input stage 400 comprises amplifyingMOSFETs “M₄” 402 and “M₅” 404, load MOSFETs “M₆” 406 and “M₇” 408,current mirror MOSFETs “M₈” 410 and “M₉” 412, and variable currentsource I_(v) 304.

Amplifying MOSFETs M₄ 402 and M₅ 404 are configured as a differentialpair with their source terminals connected together. A load MOSFET isconnected to the drain terminal of each amplifying MOSFET. The drainterminal of M₆ 406 is connected to the drain terminal of M₄ 402; thedrain terminal of M₇ 408 is connected to the drain terminal of M₅ 404.The source terminals of M₆ 406 and M₇ 408 are together connected tofirst supply voltage V_(DD) 120. The source terminals of current mirrorMOSFETs M₈ 410 and M₉ 412 are also together connected to first supplyvoltage V_(DD) 120. The gate terminal of M₈ 410 is connected to the gateand drain terminals of M₆ 406; the gate terminal of M₉ 412 is connectedto the gate and drain terminals of M₇ 408. Variable current source I_(v)304 is connected between the source terminal of M₄ 402 and M₅ 404 andanalog ground V_(AG) 118. In input stage 400, M₄ 402 and M₅ 404 areNMOSFETs, while M₆ 406, M₇ 408, M₈ 410, and M₉ 412 are PMOSFETs(p-channel MOSFETs). However, this configuration can be reverseddepending upon the overall configuration of the comparator associatedwith latch circuit 200. Furthermore, the skilled artisan will appreciatethat M₄ 402, M₅ 404, M₆ 406, M₇ 408, M₈ 410, and M₉ 412 can also berealized in other field effect, junction, or combination transistortechnologies.

The voltage of analog signal x 128 is received by input stage 400 at thenoninverting terminal of the comparator (e.g., A 102, B 104, or C 106).This allows the voltage of analog signal x 128 to be compared with areference voltage “ref” 414 received at the inverting terminal of thecomparator. For example, the voltage of analog signal x 128 is comparedwith V_(DD)/4, for comparator A 102; V_(DD)/2, for comparator B 104; and3 V_(DD)/4, for comparator C 106. The noninverting terminal of thecomparator is connected to the gate terminal of M₄ 402. The invertingterminal of the comparator is connected to the gate terminal of M₅ 404.

Amplifying MOSFETs M₄ 402 and M₅ 404 act to control the distribution ofcurrent provided by variable current source I_(v) 304. The sum of thecurrent flowing through both M₄ 402 and M₅ 404 equals the currentprovided by variable current source I_(v) 304, which is equal to twicebias current i_(b). For example, as the voltage received at the gateterminal of M₄ 402 rises with respect to the voltage received at thegate terminal of M₅ 404, the portion of the total current that flowsthrough M₄ 402 and M₆ 406 increases, while the portion of the totalcurrent that flows through M₅ 404 and M₇ 408 decreases. M₈ 410 mirrorsthe increase in current flowing through M₆ 406 to produce first currentsignal i₁ 218 at the drain terminal of M₈ 410. M₉ 412 mirrors thedecrease in current flowing through M₇ 408 to produce second currentsignal i₂ 120 at the drain terminal of M₉ 412.

Variable current source I_(v) 304 is controlled by Exclusive OR gate XOR302. When logic signal s 306 produced by Exclusive OR gate XOR 302 isone, the current produced by variable current source I_(v) 304 isincreased, which increases bias current i_(b) for latch circuit 200.Increasing bias current i_(b) increases both first and second currentsignals i₁ 218 and i₂ 220 and decreases the time needed for the port(i.e., N₄ 210 or N₅ 212) receiving the current signal (i.e., i₁ 218 ori₂ 220) that is greater than bias current i_(b) to reach its new steadystate voltage. This increases the overall speed of latch circuit 200 anddecreases the likelihood that it will remain in a metastable state.

FIG. 4B is a schematic diagram of an input stage 450 that can be usedwith latch circuit 200 in an implementation of any of comparators A 102,B 104, or C 106. Input stage 450 is configured in the same manner asinput stage 400 except that: (1) a fixed current source “2 i _(b)” 416is connected in parallel with variable current source I_(v) 304 betweenthe source terminal of M₄ 402 and M₅ 404 and analog ground V_(AG) 118,and (2) a switch “S” 418 is connected in series with variable currentsource I_(v) 304 between the source terminal of M₄ 402 and M₅ 404 andanalog ground V_(AG) 118.

Fixed current source 2 i _(b) 416 produces a current that is equal totwice bias current i_(b). Switch S 418 is controlled by Exclusive ORgate XOR 302. When logic signal s 306 produced by Exclusive OR gate XOR302 is zero, switch S 418 is opened; when logic signal s 306 produced byExclusive OR gate 302 is one, switch S 418 is closed. When switch S 418is closed, the sum of the current flowing through both M₄ 402 and M₅ 404equals the current provided by the sum of fixed current source 2 i _(b)416 and variable current source I_(v) 304. This sum current increasesboth first and second current signals i₁ 218 and i₂ 220 and decreasesthe time needed for the port (i.e., N₄ 210 or N₅ 212) receiving thecurrent signal (i.e., i₁ 218 or i₂ 220) that is greater than biascurrent i_(b) to reach its new steady state voltage. This increases theoverall speed of latch circuit 200 and decreases the likelihood that itwill remain in a metastable state.

As input stages 400 and 450 demonstrate, the skilled artisan couldconceive of any number of circuits that could increase bias currenti_(b) based on the teachings given herein. Therefore, the presentinvention is not limited to the teachings of input stages 400 and 450.

FIG. 5 is a block diagram of a portion of an array 500 of current-modecomparators configured in the manner of another embodiment of thepresent invention. The portion of array 500 comprises a comparator “O”502, comparator A 102, comparator B 104, comparator C 106, a comparator“D” 504, a comparator “E” 506, an Exclusive OR gate “XOR_(A)” 508,Exclusive OR gate XOR 302, an Exclusive OR gate “XOR_(C)” 510, anExclusive OR gate “XOR_(D)” 512, a variable current source “I_(vO)” 514,a variable current source “I_(vA)” 516, variable current source I_(v)304, a variable current source “I_(vC)” 518, a variable current source“I_(vD)” 520, and a variable current source “I_(vE)” 522.

As with array 300, the comparators, Exclusive OR gates, and variablecurrent sources of portion of array 500 are configured such that anExclusive OR gate produces a logic signal that controls a variablecurrent source that augments bias current for a latch circuit of acomparator of the array. The Exclusive OR gate receives as inputsquantized signals from other comparators of the array that are adjacenton either side of the bias current augmented comparator. Thus, theportion of array 500 expands upon the teachings of array 300 to show howthe present invention operates in an environment of multiple ExclusiveOR gates.

For example, if analog signal x 128 is nearly equal to the referencevoltage of comparator B 104, then comparators O 502 and A 102 willquickly produce quantized signals with values HIGH, and comparators C106, D 504, and E 506 will quickly produce quantized signals with valuesLOW, but comparator B 104 may be slow to produce a digital value for itsquantized signal before the end of the sampling phase.

In this situation, XOR_(A) 508, which receives inputs from comparators O502 and B 104, does not produce a digital output; XOR 302, whichreceives inputs from comparators A 102 and C 106, produces a digitaloutput of one; XOR_(C) 510, which receives its input from comparators B104 and D 504, does not produce a digital output; and XOR_(D) 512, whichreceives inputs from comparators C 106 and E 506, produces a digitaloutput of zero. Thus, XOR 302 acts to cause variable current sourceI_(v) 304 to augment bias current i_(b) for the latch circuit associatedwith comparator B 104.

If, in response to an increase in bias current i_(b) for the latchcircuit associated with comparator B 104, comparator B 104 transitionsto a new steady state of, for example, HIGH, then XOR_(A) 508 produces adigital output of zero, and XOR_(C) 510 produces a digital output ofone. Thus, XOR_(C) 510 acts to cause variable current source I_(VC) 518to augment bias current i_(b) for the latch circuit associated withcomparator C 106.

The remaining Exclusive OR gates do not cause their respective variablecurrent sources to augment the bias currents for the latch circuitsassociated with their comparators. Advantageously, this: (1) increasesthe speed of comparator B 104 and decreases the likelihood that it willremain in a metastable state, (2) reduces the BER of an ADC realizedwith array 500, and (3) limits the increase in current drawn (and hencepower dissipated) by array 500 to realize the increased speed ofcomparator B 104.

FIG. 6 is a block diagram of a portion of an array 600 of current-modecomparators configured in the manner of yet another embodiment of thepresent invention. The portion of array 600 comprises comparator O 502,comparator A 102, comparator B 104, comparator C 106, comparator D 504,comparator E 506, an Exclusive OR gate “XOR_(AB)” 602, an Exclusive ORgate “XOR_(BC)” 604, an Exclusive OR gate “XOR_(CD)” 606, variablecurrent source I_(vO) 514, variable current source I_(vA) 516, variablecurrent source I_(v) 304, variable current source I_(vC) 518, variablecurrent source I_(vD) 520, and variable current source I_(vE) 522.

The portion of array 600 expands upon the teachings of array 500 to showhow the present invention can provide the designer with a tradeoffbetween power dissipated and die area consumed. In the portion of array600, XOR_(AB) 602 receives inputs from comparators O 502 and C 106, andcontrols variable current sources I_(vA) 516 and I_(v) 304; XOR_(BC) 604receives inputs from comparators A 102 and D 504, and controls variablecurrent sources I_(v) 304 and I_(vC) 518; and XOR_(CD) 606 receivesinputs from comparators B 104 and E 506, and controls variable currentsources I_(vC) 518 and I_(vD) 520.

In this configuration, for example, if analog signal x 128 is nearlyequal to the reference voltage of comparator B 104, then comparators O502 and A 102 will quickly produce quantized signals with values HIGH,and comparators C 106, D 504, and E 506 will quickly produce quantizedsignals with values LOW, but comparator B 104 may be slow to produce adigital value for its quantized signal before the end of the samplingphase.

In this situation, XOR_(AB) 602 produces a digital output of one,XOR_(BC) 604 produces a digital output of one, and XOR_(CD) 606 does notproduce a digital output. Thus, XOR_(AB) 602 and XOR_(BC) 604 act tocause variable current sources I_(vA) 516, I_(v) 304, and I_(vC) 518 toaugment bias currents i_(b) for the latch circuits associated withcomparators A 102, B 104, and C 106.

If, in response to an increase in bias current i_(b) for the latchcircuit associated with comparator B 104, comparator B 104 transitionsto a new steady state of, for example, HIGH, then XOR_(CD) 606 producesa digital output of one. Thus, XOR_(CD) 606 acts to cause variablecurrent source I_(VD) 520 to augments bias current i_(b) for the latchcircuit associated with comparator D 504.

The remaining Exclusive OR gates do not cause their respective variablecurrent sources to augment the bias currents for the latch circuitsassociated with their comparators. Thus, for comparable realizations ofarrays 500 and 600, array 600 draws more current (and hence dissipatesmore power) than array 500. However, because array 600 uses fewerExclusive OR gates, array 600 consumes less die area than array 500.

FIG. 7 is a schematic diagram of another current-mode latch circuit 700that can be used in a realization a comparator of the present invention.Latch circuit 700 comprises latch circuit 200, a first vertical latch702 with a first vertical latch reset switch 704, a second verticallatch 706 with a second vertical latch reset switch 708, and a secondpair of cross connected transistors 710.

First vertical latch 702 is connected between analog ground V_(AG) 118and first supply voltage V_(DD) 120. Preferably, first vertical latch702 comprises a fourth NMOSFET “M₁₀” 712 and a first PMOSFET “M₁₁” 714,where M₁₀ 712 and M₁₁ 714 are matched transistors. Preferably, each ofM₁₀ 712 and M₁₁ 714 has a gain greater than one. However, first verticallatch 702 can function if the product of the individual gains of M₁₀ 712and M₁₁ 714 (i.e., the loop gain) is greater than one. The sourceterminal of M₁₀ 712 is connected to analog ground V_(AG) 118. The drainterminal of M₁₀ 712 is connected to the gate terminal of M₁₁ 714. Thegate terminal of M₁₀ 712 is connected to the gate terminal of M₂ 208.The source terminal of M₁₁ 714 is connected to first supply voltageV_(DD) 120. The drain terminal of M₁₁ 714 is connected to the gateterminal of M₁₀ 712. The skilled artisan will appreciate that M₁₀ 712and M₁₁ 714 can also be realized in other field effect, junction, orcombination transistor technologies.

Preferably, first vertical latch reset switch 704 comprises a secondPMOSFET “M₁₂” 716. The source terminal of M₁₂ 716 is connected to firstsupply voltage V_(DD) 120. The drain terminal of M₁₂ 716 is connected tothe gate terminal of M₁₁ 714. An inverse clock waveform “Ck.bar” 718 isapplied to the gate terminal of M₁₂ 716. Ck.bar 718 cycles between DOWNvoltage and UP voltage at the sampling frequency in a manner such thatwhen the voltage of Ck 216 is UP, the voltage of Ck.bar 718 is DOWN, andvice versa. The skilled artisan will appreciate that M₁₂ 716 can also berealized in other field effect, junction, or combination transistortechnologies. In general, first vertical latch reset switch 704 can berealized in a variety of switch technologies, includingmicroelectromechanical embodiments.

Second vertical latch 706 is connected between analog ground V_(AG) 118and first supply voltage V_(DD) 120. Preferably, second vertical latch706 comprises a fifth NMOSFET “M₁₃” 720 and a third PMOSFET “M₁₄” 722,where M₁₃ 720 and M₁₄ 722 are matched transistors. Preferably, each ofM₁₃ 720 and M₁₄ 722 has a gain greater than one. However, secondvertical latch 706 can function if the product of the individual gainsof M₁₃ 720 and M₁₄ 722 (i.e., the loop gain) is greater than one. Thesource terminal of M₁₃ 720 is connected to analog ground V_(AG) 118. Thedrain terminal of M₁₃ 720 is connected to the gate terminal of M₁₄ 722.The gate terminal of M₁₃ 720 is connected to the gate terminal of M₁206. The source terminal of M₁₄ 722 is connected to first supply voltageV_(DD) 120. The drain terminal of M₁₄ 722 is connected to the gateterminal of M₁₃ 720. The skilled artisan will appreciate that M₁₃ 720and M₁₄ 722 can also be realized in other field effect, junction, orcombination transistor technologies.

Preferably, second vertical latch reset switch 708 comprises a fourthPMOSFET “M₁₅” 724. The source terminal of M₁₅ 724 is connected to firstsupply voltage V_(DD) 120. The drain terminal of M₁₅ 724 is connected tothe gate terminal of M₁₄ 722. Inverse clock waveform Ck.bar 506 isapplied to the gate terminal of M₁₅ 724. The skilled artisan willappreciate that M₁₃ 720, M₁₄ 722, and M₁₅ 724 can also be realized inother field effect, junction, or combination transistor technologies. Ingeneral, second vertical latch reset switch 708 can be realized in avariety of switch technologies, including microelectromechanicalembodiments.

Preferably, second cross connected pair 710 comprises a fifth PMOSFET“M₁₆” 726 and a sixth PMOSFET “M₁₇” 728, where M₁₆ 726 and M₁₇ 728 arematched transistors. Preferably, each of M₁₆ 726 and M₁₇ 728 has a gaingreater than one. However, second cross connected pair 710 can functionif the product of the individual gains of M₁₆ 726 and M₁₇ 728 (i.e., theloop gain) is greater than one. The gate terminal of M₁₇ 728 isconnected to the drain terminal of M₁₆ 726 and to the gate terminal ofM₁₄ 722. The gate terminal of M₁₆ 726 is connected to the drain terminalof M₁₇ 728 and to the gate terminal of M₁₁ 714. The source terminals ofM₁₆ 726 and M₁₇ 728 are together connected to first supply voltageV_(DD) 120. The skilled artisan will appreciate that M₁₆ 726 and M₁₇ 728can also be realized in other field effect, junction, or combinationtransistor technologies.

First vertical latch 702 and second vertical latch 706 act to increasethe rate at which the port (i.e., N₄ 210 or N₅ 212) receiving thecurrent signal (i.e., i₁ 218 or i₂ 220) that is greater than biascurrent i_(b) reaches its new steady state voltage.

For example, when the voltage of Ck 216 is DOWN (i.e., the samplingphase), the states of M₁ 206 and M₂ 208 are controlled by first andsecond current signals i₁ 218 and i₂ 220. If first current signal i₁ 218is greater than bias current i_(b), first current signal i₁ 218continues to charge the parasitic capacitances at N₄ 210, which causesthe voltage at N₄ 210 to rise. Contemporaneously, when second currentsignal i₂ 220 is less than bias current i_(b), the parasiticcapacitances at N₅ 212 start to discharge, which causes the voltage atN₅ 212 to drop.

Because the voltage at N₅ 212 is also the voltage at the gate terminalof M₁ 206, the voltage at the gate terminal of M₁ 206 drops by the sameamount as the drop in the voltage at N₅ 212. Because the voltage at thesource terminal of M₁ 206 is held at analog ground V_(AG) 118, thegate-to-source voltage of M₁ 206 decreases by the same amount as thedrop in the voltage at the gate terminal of M₁ 206. The decrease in thegate-to-source voltage of M₁ 206 causes its drain current to decrease.In response to the decrease in the gate-to-source voltage of M₁ 206 andthe decrease in its drain current, the drain-to-source voltage of M₁ 206increases by a greater magnitude than the decrease in its gate-to-sourcevoltage.

Meanwhile, because the voltage at N₄ 210 is also the voltage at the gateterminal of M₂ 208, the voltage at the gate terminal of M₂ 208 rises bythe same amount as the rise in the voltage at N₄ 210. Likewise, becausethe voltage at N₄ 210 is also the voltage at the gate terminal of M₁₀712, the voltage at the gate terminal of M₁₀ 712 rises by the sameamount as the rise in the voltage at N₄ 210.

Because the voltage at the source terminal of M₂ 208 is held at analogground V_(AG) 118, the gate-to-source voltage of M₂ 208 increases by thesame amount as the rise in the voltage at the gate terminal of M₂ 208.The increase in the gate-to-source voltage of M₂ 208 causes its draincurrent to increase. In response to the increase in the gate-to-sourcevoltage of M₂ 208 and the increase in its drain current, thedrain-to-source voltage of M₂ 208 decreases by a greater magnitude thanthe increase in its gate-to-source voltage. Likewise, because thevoltage at the source terminal of M₁₀ 712 is held at analog groundV_(AG) 118, the gate-to-source voltage of M₁₀ 712 increases by the sameamount as the rise in the voltage at the gate terminal of M₁₀ 712. Theincrease in the gate-to-source voltage of M₁₀ 712 causes its draincurrent to increase. In response to the increase in the gate-to-sourcevoltage of M₁₀ 712 and the increase in its drain current, thedrain-to-source voltage of M₁₀ 712 decreases by a greater magnitude thanthe increase in its gate-to-source voltage.

Because the voltage at the source terminal of M₁₀ 712 is held at analogground V_(AG) 118, the decrease in the drain-to-source voltage of M₁₀712 causes the voltage at the voltage at the drain terminal of M₁₀ 712to drop by the same amount. Because the voltage at the drain terminal ofM₁₀ 712 is also the voltage at the gate terminal of M₁₁ 714, the voltageat the gate terminal of M₁₁ 714 drops by the same amount as the drop inthe voltage at the drain terminal of M₁₀ 712. Because the voltage at thesource terminal of M₁₁ 714 is held at first supply voltage V_(DD) 120,the drop in the voltage at the gate terminal of M₁₁ 714 (i.e., aPMOSFET) causes its gate-to-source voltage to increase by the sameamount. The increase in the gate-to-source voltage of M₁₁ 714 causes itsdrain current to increase. In response to the increase in thegate-to-source voltage of M₁₁ 714 and the increase in its drain current,the drain-to-source voltage of M₁₁ 714 decreases by a greater magnitudethan the increase in its gate-to-source voltage.

Because the voltage at the source terminal of M₂ 208 is held at analogground V_(AG) 118, the voltage at N₅ 212 drops by the same amount as thedecrease in drain-to-source voltage of M₂ 208. Thus, the voltage at N₅212 drops under the relatively small effect of second current signal i₂220 being less than bias current i_(b), and the relatively large effectof the decrease in the drain-to-source voltage of M₂ 208.

Because the voltage at N₄ 210 is also the voltage at the drain terminalof M₁₁ 714 and because the voltage at the source terminal of M₁₁ 714 isheld at first supply voltage V_(DD) 120, the voltage at N₄ 210 rises bythe same amount as the decrease in the drain-to-source voltage of M₁₁714. Furthermore, because the voltage at the source terminal of M₁ 206is held at analog ground V_(AG) 118, the voltage at N₄ 210 rises by thesame amount as the increase in drain-to-source voltage of M₁ 206.Additionally, because the voltage at the source terminal of M₁₁ 714 isheld at first supply voltage V_(DD) 120, the voltage at N₄ 210 alsorises by the same amount as the decrease in drain-to-source voltage ofM₁₁ 714 (i.e., a PMOSFET). Thus, the voltage at N₄ 210 rises under therelatively small effect of first current signal i₁ 218 being greaterthan bias current i_(b), the relatively large effect of the increase inthe drain-to-source voltage of M₁ 206, and the relatively larger effectof the decrease in the drain-to-source voltage of M₁₁ 714.

The increasing of the drain-to-source voltage of M₁ 206 and thedecreasing of the drain-to-source voltage of M₂ 208 reinforce eachother. The gate-to-source voltage of M₁ 206 decreases with thedrain-to-source voltage of M₂ 208 until M₁ 206 is turned OFF.

When M₁ 206 is OFF, it does not conduct current. Without drain current,the decreasing of the gate-to-source voltage of M₁ 206 no longer effectsits drain-to-source voltage. However, the voltage at N₄ 210 continues torise under the relatively small effect of first current signal i₁ 218being greater than bias current i_(b) and the relatively larger effectof the decrease in the drain-to-source voltage of M₁₁ 714 until theparasitic capacitances at N₄ 210 are fully charged and the voltage at N₄210 is HIGH.

It will be recognized that M₁₀ 712 and M₁₁ 714 form a positive feedbackloop that amplifies first current signal i₁ 218 and applies anexponentially growing current to the drain terminal of M₁ 206. Thus, theparasitic capacitances at N₄ 210 are charged under the combined effectsof first current signal i₁ 218 and the exponentially growing currentdrawn from first supply voltage V_(DD) 120 by M₁₁ 714.

First vertical latch reset switch 704 and second vertical latch resetswitch 708 act to reduce the power dissipated by, respectively, firstvertical latch 702 and second vertical latch 706 during the reset phase.For example, when the voltage of Ck.bar 718 is DOWN (i.e., the resetphase), M₁₂ 716 (i.e., a PMOSFET) connects the gate terminal of M₁₁ 714to first supply voltage V_(DD) 120. With the gate and source terminalsof M₁₁ 714 connected together, the gate-to-source voltage of M₁₁ 714 ismade to equal zero, Holding M₁₁ 714 OFF. This disrupts the latchingaction of first vertical latch 702 so that cross connected pair 202 canassume a state independent of the state of first vertical latch 702.

However, after the start of the sampling phase, the gate-to-sourcevoltages of M₁₂ 716 and M₁₅ 724 (i.e., PMOSFETs) can drift to valuesgreater than their threshold voltages such that M₁₁ 714 and M₁₄ 722 turnON. Having M₁ 206, M₂ 208, M₁₀ 712, M₁₁ 714, M₁₃ 720, and M₁₄ 722 all ONbefore the MOSFETs change states can cause latch circuit 700 to draw alarge amount of current. Latch circuit 700 acts, in response to firstand second current signals i₁ 218 and i₂ 220, to force one MOSFET ofsecond cross connected pair 710 (e.g., M₁₆ 726) ON while the otherMOSFET of second cross connected pair 710 (e.g., M₁₇ 728) remains OFF.The MOSFET of second cross connected pair 710 (e.g., M₁₆ 726) that turnsON connects the gate terminal of its corresponding vertical latch MOSFET(e.g., M₁₁ 714) to first supply voltage V_(DD) 120. With the gate andsource terminals of the corresponding vertical latch MOSFET connectedtogether, the gate-to-source voltage of the corresponding vertical latchMOSFET is made to equal zero, holding the corresponding vertical latchMOSFET OFF. In this manner, second cross connected pair 710 acts toprevent latch circuit 700 from drawing unnecessary current before theMOSFETs change states during the sampling phase.

For example, when, at the start of the sampling phase, first currentsignal i₁ 218 is slightly larger than bias current i_(b) (i.e., smallpositive signal current i_(s)), then first current signal i₁ 218 slowlycontinues to charge the parasitic capacitances at N₄ 210, which causesthe voltage at N₄ 210 to rise slightly. Because the voltage at N₄ 210 isalso the voltage at the gate terminal of M₁₀ 712, the voltage at thegate terminal of M₁₀ 712 rises by the same amount as the rise in thevoltage at N₄ 210.

Because the voltage at the source terminal of M₁₀ 712 is held at analogground V_(AG) 118, the gate-to-source voltage of M₁₀ 712 increases bythe same amount as the rise in the voltage at the gate terminal of M₁₀712. The increase in the gate-to-source voltage of M₁₀ 712 causes itsdrain current to increase. In response to the increase in thegate-to-source voltage of M₁₀ 712 and the increase in its drain current,the drain-to-source voltage of M₁₀ 712 decreases by a greater magnitudethan the increase in its gate-to-source voltage. Because the voltage atthe source terminal of M₁₀ 712 is held at analog ground V_(AG) 118, thedecrease in the drain-to-source voltage of M₁₀ 712 causes the voltage atthe drain terminal of M₁₀ 712 to drop by the same amount.

Because the voltage at the drain terminal of M₁₀ 712 is also the voltageat the gate terminal of M₁₆ 726, the voltage at the gate terminal of M₁₆726 drops by the same amount as the drop in the voltage at the drainterminal of M₁₀ 712.

Because the voltage at the source terminal of M₁₆ 726 is held at firstsupply voltage V_(DD) 120, the drop in the voltage at the gate terminalof M₁₆ 726 (i.e., a PMOSFET) causes its gate-to-source voltage toincrease by the same amount. The increase in the gate-to-source voltageof M₁₆ 726 causes its drain current to increase. In response to theincrease in the gate-to-source voltage of M₁₆ 726 and the increase inits drain current, the drain-to-source voltage of M₁₆ 726 decreases by agreater magnitude than the decrease in its gate-to-source voltage.Because the voltage at the source terminal of M₁₆ 726 is held at firstsupply voltage V_(DD) 120, the decrease in the drain-to-source voltageof M₁₆ 726 (i.e., a PMOSFET) causes the voltage at the drain terminal ofM₁₆ 726 to rise by the same amount.

Because the voltage at the drain terminal of M₁₆ 726 is also the voltageat the gate terminal of M₁₄ 722, the voltage at the gate terminal of M₁₄722 rises by the same amount as the rise in the voltage at the drainterminal of M₁₆ 726. Because the voltage at the source terminal of M₁₄722 is held at first supply voltage V_(DD) 120, the rise in the voltageat the gate terminal of M₁₄ 722 (i.e. a PMOSFET) causes itsgate-to-source voltage to decrease by the same amount.

The decrease in the gate-to-source voltage of M₁₄ 722 ensures that it isless than its threshold voltage so that M₁₄ 722 is held OFF. Having M₁₄722 held OFF until first current signal i₁ 218 charges the parasiticcapacitances at N₄ 210 to its new steady state voltage of HIGH preventslatch circuit 700 from drawing unnecessary current during the samplingphase.

For an ADC that incorporates an array of comparators based on latchcircuit 700, in which the parameters that define latch circuit 700(i.e., supply voltages, clock frequency, etc.) had specific values,where the ADC was configured with Exclusive OR gates in the manner ofthe present invention, simulation showed an improvement in the BER from10⁻⁵⁰ to 10⁻¹⁰⁰. Latch circuit 700 is further described in applicationSer. No. 10/083,463, filed on Feb. 27, 2002, which is incorporatedherein by reference.

Although the present invention is described in relation to comparatorsrealized with current-mode latch circuits, the skilled artisan willappreciate that the teachings of the present invention are not limitedto this embodiment. A signal based on any characteristic (e.g., voltage,resistance, etc.) that indicates that a comparator is in a steady statecan be used in an embodiment of the present invention to identify acomparator in a metastable condition. Indeed, such a signal need not bethe output of the comparator. Therefore, the present invention is notlimited to current-mode latch circuit comparator embodiments.

FIG. 8 shows a flow chart of a method 800 for increasing, in an array ofcomparators, a rate at which a comparator in a metastable conditiontransitions to a steady state. In method 800, at a step 802, thecomparator in the metastable condition in the array of comparators isidentified. At a step 804, a bias current is provided to the identifiedcomparator in the metastable condition, such that the rate at which thecomparator in the metastable condition transitions to the steady stateis increased. Preferably, the bias current is provided by controlling acurrent output from a variable current source that provides the biascurrent for a latch circuit of the identified comparator in themetastable condition.

To further explain step 802, FIG. 9 shows a flow chart of a preferredmethod to identify the comparator in the metastable condition. At a step902, a characteristic of a first comparator of the array of comparatorsis compared with a characteristic of a second comparator of the array ofcomparators. The first comparator and the second comparator areseparated in the array of comparators by a third comparator in the arrayof comparators. At a step 904, it is determined if the third comparatoris the comparator in the metastable condition based on the comparedcharacteristics. Preferably, the characteristics are compared byreceiving the characteristics as inputs to an Exclusive OR gate.

In an embodiment, the bias current is provided by controlling a currentoutput from a variable current source that provides the bias current fora latch circuit of the identified comparator in the metastable conditionwith an output of an Exclusive OR gate.

In another embodiment, the bias current is provided by connecting afirst current source in parallel with a second current source toincrease the bias current for a latch circuit of the identifiedcomparator in the metastable condition. Preferably, a switch thatconnects the first current source in parallel with the second currentsource is controlled by an output of an Exclusive OR gate.

FIG. 10 shows a flow chart of a method 1000 for increasing, in an arrayof comparators that includes a first, a second, and a third comparator,a rate at which the third comparator transitions to a steady state. Inmethod 1000, at a step 1002, an output of the first comparator iscompared with an output of the second comparator. At a step 1004, a biascurrent is provided to the third comparator.

In an embodiment, the outputs are compared by receiving the first andsecond outputs as inputs to an Exclusive OR gate. Preferably, a variablecurrent source that provides the bias current for a latch circuit of thethird comparator is controlled based on an output of an Exclusive ORgate.

In another embodiment, the bias current is provided to the thirdcomparator by connecting a first current source in parallel with asecond current source to increase the bias current for a latch circuitof the third comparator. Preferably, a switch that connects the firstcurrent source in parallel with the second current source is controlledbased on an output of an Exclusive OR gate.

Preferably, the bias current is provided by controlling a current outputfrom a variable current source that provides the bias current for alatch circuit of the identified comparator in the metastable condition.

CONCLUSION

While various embodiments of the present invention have been describedabove, it should be understood that they have been presented by way ofexample, and not limitation. It will be apparent to persons skilled inthe relevant art that various changes in form and detail can be madetherein without departing from the spirit and scope of the invention.Thus the present invention should not be limited by any of theabove-described exemplary embodiments, but should be defined only inaccordance with the following claims and their equivalents.

1. In an array of comparators, a method for increasing a rate at which acomparator in a metastable condition transitions to a steady state,comprising the steps of: (1) identifying, in the array of comparators,the comparator in the metastable condition; and (2) providing a biascurrent to said identified comparator in the metastable condition, suchthat the rate at which the comparator in the metastable conditiontransitions to the steady state is increased.
 2. The method of claim 1,wherein said providing step comprises the step of: controlling a currentoutput from a variable current source that provides the bias current fora latch circuit of said identified comparator in the metastablecondition.
 3. The method of claim 1, wherein said identifying stepcomprises the steps of: (a) comparing a characteristic of a firstcomparator of the array of comparators with a characteristic of a secondcomparator of the array of comparators, wherein the first comparator andthe second comparator are separated in the array of comparators by athird comparator in the array of comparators; and (b) determining if thethird comparator is the comparator in the metastable condition based onsaid compared characteristics.
 4. The method of claim 3, wherein saidcomparing step comprises the step of: receiving the characteristics asinputs to an Exclusive OR gate.
 5. The method of claim 4, said providingstep comprises the step of: controlling a current output from a variablecurrent source that provides the bias current for a latch circuit ofsaid identified comparator in the metastable condition with an output ofthe Exclusive OR gate.
 6. In an array of comparators, a method forincreasing a rate at which a comparator in a metastable conditiontransitions to a steady state, comprising the steps of: (1) comparing acharacteristic of a first comparator of the array of comparators with acharacteristic of a second comparator of the array of comparators byreceiving the characteristics as inputs to an Exclusive OR gate, whereinthe first comparator and the second comparator are separated in thearray of comparators by a third comparator in the array of comparators;(2) determining if the third comparator is the comparator in themetastable condition based on said compared characteristics; and (3)connecting a first current source in parallel with a second currentsource to increase the bias current for a latch circuit of saiddetermined comparator in the metastable condition.
 7. The method ofclaim 6, further comprising the step of: controlling a switch thatconnects the first current source in parallel with the second currentsource with an output of the Exclusive OR gate.
 8. In an array ofcomparators that includes a first, a second, and a third comparator, amethod for increasing a rate at which the third comparator transitionsto a steady state, comprising the steps of: (1) comparing an output ofthe first comparator with an output of the second comparator; and (2)providing a bias current to the third comparator based on said comparedfirst and second outputs.
 9. The method of claim 8, wherein saidcomparing step comprises the step of: receiving the first and secondoutputs as inputs to an Exclusive OR gate.
 10. The method of claim 9,wherein said providing step comprises the step of: controlling avariable current source that provides the bias current for a latchcircuit of the third comparator based on an output of the Exclusive ORgate.
 11. In an array of comparators that includes a first, a second,and a third comparator, a method for increasing a rate at which thethird comparator transitions to a steady state, comprising the steps of:(1) comparing an output of the first comparator with an output of thesecond comparator; and (2) providing a bias current to the thirdcomparator based on said compared first and second outputs by connectinga first current source in parallel with a second current source toincrease the bias current for a latch circuit of the third comparator.12. The method of claim 11, further comprising the step of: controllinga switch that connects the first current source in parallel with thesecond current source based on an output of an Exclusive OR gate.